1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a static random access memory and a method for fabricating the same.
2. Background of the Related Art
A related art method for fabricating a semiconductor memory device will be explained with reference to the attached drawings. FIG. 1 illustrates a circuit of a general SRAM cell, and FIGS. 2a-2c illustrate sections across an access transistor TA and a drive transistor TD in an SRAM showing steps of a related art method for fabricating the SRAM.
Referring to FIG. 2a, an active region and a field region are defined on a semiconductor substrate 1, and a field insulating film 2 is formed on the field region. An oxide film is deposited on the entire surface to form a gate oxide film 3. A Buried Contact (BC) region 4 for connecting a first cell node CN1 to a gate electrode for a second drive transistor is defined, wherefrom the gate oxide film 3 is removed. As shown in FIG. 2b, n.sup.+ impurity ions are injected into the semiconductor substrate 1 in the buried contact region 4 to form an n.sup.+ impurity region 5 therein. A polysilicon layer is deposited on the entire surface and predetermined regions thereof are patterned to form a gate electrode 6b for the access transistor and a gate electrode 6a for the drive transistor. In this instance, the gate electrode 6a for the drive transistor is formed to be in contact with the n.sup.+ impurity region 5 in the buried contact region. Portions of the semiconductor substrate 1 on both sides of the gate electrode 6b for the access transistor are lightly doped with n type impurity ions to form LDD regions 7 therein.
As shown in FIG. 2c, an oxide film is deposited on the entire surface, and etched back to form sidewall insulating films 8 at both sides of the gate electrode 6b for the access transistor and the gate electrode 6a for the drive transistor. Portions of the semiconductor substrate 1 on both sides of the gate electrode 6b for the access transistor and the gate electrode 6a for the drive transistor are heavily doped with n type impurity ions to form source/drain regions 9. An interlayer insulating film 10 is deposited on the entire surface, and portions of the gate oxide film 4 and the interlayer insulating film 10 on one side of the gate transistor 6a for the drive transistor, i.e., one side of the buried contact region 4 over the source/drain region 9 is subjected to anisotropic etching to form a contact hole therein. An undoped polysilicon layer is deposited on the entire surface and subjected to patterning to be in contact with the source/drain region 9 to form a load polysilicon layer 11.
The operation to write a value of "1" on the first cell node CN1 in the general SRAM cell will be explained with reference to FIG. 1. In general, to write a data on a cell, a word line (W/L) is applied with a voltage of 5 V to turn on a first access transistor TA1 and a second access transistor TA2. Then, the data intended to store is applied to a bit line and a bit bar line. Consequently, data on the bit line B/L and the bit bar line /B/L can be stored in the first cell node CN1 and the second cell node CN2 through the first access transistor TA1 and the second access transistor TA2, respectively. The voltage stored in the first cell node CN1 can be expressed as V.sub.CN1 =V.sub.CC -Vth'(TA1), where, Vth'(TA1) is a threshold voltage increased by a back bias effect of the first access transistor TA1. For example, when V.sub.CC =5 V, the voltage stored in the first cell node CN1 is V.sub.CN1 =5-1.5=3.5 V.
However, the related art method for fabricating a semiconductor memory device has various problems. For example, the higher the threshold voltage of the access transistor and higher back bias voltage Vth'(TA1) cause an instable operation of the SRAM at a low voltage.